FFT algorithm is frequently used to orthogonal frequency division multiplexing (OFDM) system and OFDM is widely applied to various communication systems in recent years, especially to wireless communication system, so that many communication-related researches on FFT processor have been developed substantially. FFT generally has two kinds of hardware design, one is non-pipelined and another is pipelined. Non-pipelined FFT, essentially adopting a main memory unit and a few butterfly computation processors, reads data out from main memory unit and processes them in order, in which computation of overall data at a same stage must be completed before performing computation of next stage. However, when non-pipelined method is applied to OFDM system, the data which is going to be processed needs to be pre-stored in memory and it is required to add an extra memory for temporarily storing new input data to enable parallel data input and processing able to process continuous input data. Compared to non-pipelined design, pipelined FFT design adapts for use in continuous single-input data system rather than non-pipelined design, the reason is that pipelined FFT design adds data switch composed of memory unit between process units of each stage to pre-order computation results of last stage to be suitable for data-processing sequence of next stage.
FIG. 1 shows a known Multi-Path Delay Feedback (MDF) type pipelined FFT, which can provide higher data throughput rate. However, because input data of the first half is prearranged and temporarily stored into memory in order to facilitate processing data at first stage, only 50% of hardware can be used for processing data and N/2 more internal buffer area is required to reset input data, that makes overall buffer area increase to total amount of
      W    ×                  3        ⁢                                  ⁢        N            2        ,where N represents sample number, W represents bit length of input data. Besides, overall output data obtained from computation of performing pipelined FFT are in special bit-reversal output sequence, so an extra output sequence converter is added to transform the bit-reversal output sequence of final stage to a general output sequence in applicable condition, but an extra cost is increased.